1. Field of the Invention
The present invention relates to techniques to increase hierarchical compression for the metal one layer of an integrated circuit during optical proximity correction (OPC).
2. Related Art
In designing an integrated circuit (IC), engineers typically rely upon computer simulation tools to help create a circuit schematic design consisting of circuits coupled together to perform certain complex functions. For application specific ICs (ASICs), these tools can use standard cells to implement the circuits. To actually fabricate this design on an IC layer of a wafer, the design can be translated into a physical representation or layout. Typically, to perform this translation, automated layout tools can be used to place and interconnect the standard cells.
Once the layout of the circuit has been created, the next step to manufacturing the IC is to transfer the layout onto an IC layer. Optical lithography can perform this transfer, i.e. the layout is first transferred onto a physical template (e.g. a mask) which is in turn used to optically project the layout onto the IC layer.
In transferring the layout to the physical template, a mask (e.g. a quartz plate coated with chrome) is generally created for each layer of the IC design. To create a mask, the data representing the layout design for that layer can be input into a device, such as an electron beam machine, which writes the IC layout pattern into the mask material. In less complicated and dense integrated circuits, each mask comprises the geometric shapes which represent the desired circuit pattern for its corresponding layer. In more complicated and dense circuits in which the size of the circuit features approach the optical limits of the lithography process, the masks may also comprise optical proximity correction (OPC) features.
Optical proximity correction (OPC) applies systematic changes to geometries of the layout to improve the printability of a wafer pattern. Specifically, as the size of integrated circuit features drops to 0.18μ and below, the features can become smaller than the wavelength of the light used to create such features, thereby creating lithographic distortions when printing the features onto the IC layer of the wafer. These lithographic distortions can represent significant impacts on device performance.
The OPC-corrected masks can then be used to optically project the layout onto the IC layer coated with photoresist material. For each layer of the design, a light is shone on the mask corresponding to that layer via a visible light source or an ultra-violet light source. This light passes through the clear regions of the mask, whose image exposes the underlying photoresist layer. The light is blocked by the opaque regions of the mask, thereby leaving that underlying portion of the photoresist layer unexposed. The exposed photoresist layer is then developed, typically, through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is an IC layer exhibiting the desired pattern that defines the geometries, features, lines, and shapes of that layer. This process is then repeated for each IC layer of the design.
Chip layouts for ICs can be intrinsically repetitive. Identifying repeating structures with the same context determination can be used in reducing the volume of information in the layout that needs to be processed. The context determination refers to an ambit (i.e. a distance used by the optical model) and identifying differences in context within this ambit. For example, once a repeating structure (having the same context determination) is identified, determining how to process that structure need only be done once. In some layouts, repeating structures could be instantiated hundreds of thousands of times. Thus, identifying repeating structures can dramatically reduce processing time of a layout.
As described in U.S. Pat. No. 6,807,663, which is incorporated by reference in its entirety, representative repeating structures can be pre-processed for OPC, thereby taking advantage of the repetitions in the layout. Advantageously, by limiting OPC computation to representative repeating structures and instantiating other repeating structures, process speed can be significantly increased while simultaneously decreasing disk/memory requirements. Unfortunately, not all IC layers can take advantage of this pre-processing.
In particular, metal 1 (i.e. the first metal layer to be patterned in an IC) is typically the slowest IC layer to correct for OPC because the metal 1 layer does not leverage a standard cell layout. That is, slight variations in cell patterns (as determined by an OPC engine) as well as landing pad locations (as determined by a place and route tool) typically result in almost all cells as being identified as unique rather than repetitive. Therefore, metal 1 currently runs flat, i.e. without the advantages inherent for hierarchy. As a result, OPC corrections for standard cells of a metal 1 layout can be extremely time-consuming, thereby resulting in a major bottleneck for the latest technology nodes. Therefore, a need arises for metal 1 techniques that can more effectively leverage a standard cell layout.